Field of the Invention
The present invention relates a method of manufacturing a semiconductor device having a structure in which two kinds of different substrates are bonded.
Description of the Related Art
As one of semiconductor packaging technologies, a wafer-level chip-size package (WLCSP) is known. The WLCSP is a technique to package a wafer and cut and dice the wafer into semiconductor devices. Generally, the WLCSP includes a step of bonding a semiconductor substrate having a semiconductor element formed on a surface thereof to a support substrate through an adhesive layer. However, such a semiconductor substrate and support substrate often have different coefficients of thermal expansion, and the semiconductor substrate sometimes warps upon bonding. This warpage causes insufficient suction of the semiconductor substrate onto a wafer stage or the like in a subsequent step such as dicing, and manufacturing yield decreases disadvantageously.
In order to solve such a problem, for example, in Japanese Patent Application Laid-Open No. 2010-238729, stress relief grooves are formed along grid lines for cutting out and dicing semiconductor devices to inhibit warpage caused by bonding, for improved yield.
However, as described in Japanese Patent Application Laid-Open No. 2010-238729, etching the stress relief grooves along the grid lines to a level of a support substrate causes exposure of an adhesive layer before an insulating film is deposited along the stress relief grooves. Normally, a cleaning step is performed after etching a stress relief grooves and before deposition of an insulating film, but the above configuration may cause intrusion of chemical or water from the exposed adhesive layer into a semiconductor substrate, and deterioration of an electrical characteristic of the semiconductor device.